RIOS Lab Student was Invited to Give a Talk at RISC-V Summit Europe


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RIOS Lab student Yifei Zhu was invited to give a talk on GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations at RISC-V Summit Europe. She introduced the background and shared her experience on this project.

Fig.1 Yifei Zhu gave a talk at RISC-V Summit Europe

Fig.3 Group photo of RIOS Lab Students and RISC-V Foundation CEO Calista Redmond


Traditional fabrication methods often require large margins to ensure functional performance, But the adoption of public tool chains and open PDK can recycle these margins by the wisdom of the masses. Because, EDA licenses will no longer serve as a bottleneck to design space exploration in this field.

Therefore, we are trying to answer whether the open EDA tools are competent for building a modern processor? What’s the gap between open and proprietary ASIC fabrication flow? That’s why we build GreenRio, a RISC-V core with modern processors characteristics.

Through building such non-toy-like design, we optimized the OpenEDA along with the RISC-V architecture together and explore every stage of this flow.

Fig.2  Milestone of GreenRio

GreenRio1.0 is a 7-stage, dual-issue, out-of-order (OoO) processor. We demonstrated it in the efabless OpenMPW-7 program using the Skywater 130nm process. Related works were accepted by the Workshop on Open-Source EDA Technology (WOSET) as well as RISC-V Days Tokyo 2022 Autumn2. Greenrio 2.0 adds more hardware supports allowing for running applications. GreenRio2.0 has won the ISSCC Code-a-Chip competition and is becoming a benchmark in the OpenEDA domain.

User Experience of Open Toolchains

One of the challenges that the community faces is the gap between open and proprietary tools in terms of QoR and runtime. So We quantified this gap by hardening GreenRio. We used open EDA Tools: OpenROAD/OpenLANE versus appropriate EDA tools: Genus/Design Compiler/Innovus to harden this design.

We can concluded that:

  1. The open pdk lack of process corners and key parameters for timing optimization, also exists bugs
  2. Compared to propriety tools, the open one is not complete enough and needs further optimization
  3. For logic synthesis, propriety tools bring about smaller area, less gate count and lower leakage power. But the open tools win in synthesis time and can get time convergence netlists without human adjustment.
  4. For physical implementation, compared to Innovus, open tools cannot achieve higher core utilization and higher cell density. Currently, it is inferior in both runtime and performance, because its placement/routing engines are out-of-date.
  5. For the runtime allocation, open tools spend most of the time in routing, but the other one puts more effort in placement.

Fig.3  Different macro placement

RIOS Lab Students Won the 1st Place in the First “Code-A-Chip” Competition of ISSCC 2023!

2/19 – 2/23
San Francisco, CA

The International Solid-State Circuits Conference (ISSCC) is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip.

Fig.1 Group photo of the winning teams and organizers.

The Code-a-Chip competition was sponsored by the CHIPS Alliance and Google.

The student team of the RISC-V Open Source (RIOS) Lab, is the first place winner in the inaugural international Code-a-Chip competition. They presented their project GreenRio 2 at the ISSCC 2023, along with 6 other design teams from around the world. GreenRio 2 is an open-source Linux-compatible RISC-V processor developed using a complete open-source flow.

Fig.2 “Code-a-chip” winner list

Fig.3 Rob Mains, General Manager, CHIPS Alliance
Tim Ansell, General Manager, Google OpenPDK/EDA
Dr. Zhangxi Tan, Co-director, RIOS Lab

Never before has such a large global community gathered together to come up with a complete open RISC-V instruction set providing a solid foundation for architecture and silicon innovations. With the advent of openEDA and openPDK, building an open microprocessor that can run lots of real software is possible with a pure open-source tool and manufacturing flow.

Because of the maturity and limited support of openEDA, many microprocessors taped out in the past 600+ designs on Google OpenMPWs are only 32-bit MCU-class simple processors. RIOS Rio series RISC-V processors (open source under the Apache 2.0 license) on the other hand include all necessary architecture and performance features to run a full 64-bit operating system like Linux and many real-world software.

At ISSCC, RIOS team presented the design of GreenRio 2, and its open-source design flow. GreenRio 2 is an improvement from the previous version 1.0, which has already been validated in the Google/Skywater OpenMPW-7 tapeout November last year. GreeRio 1.0 is already the most complex processor design that has ever been fabricated by all past Google/SkyWater OpenMPW shuttle runs.

Fig.4 Architecture of GreenRio v2.0

Figure 4 shows the microarchitecture of the GreenRio 2 CPU pipeline. It employs a dual-issue 7-stage out-of-order architecture supporting the RV64ICMA unprivileged RISC-V ISA. It also supports Zicsr, Zifencei and Sfence.vma privileged extensions as well as the S, M and U privilege mode. GreenRio 2 is written in openEDA friendly synthesizable Verilog.

Synthesized with the latest version of OpenLane, the gate count of a single GreenRio 2.0 CPU pipeline is slightly over 230K on the Skywater 130nm process. The area is 15.87 mm^2 at a frequency of 25 MHz.

With the close collaboration between RIOS and Google along with helps from the OpenEDA tool community, GreenRio 2 pushes the design complexity limit that OpenMPW and OpenEDA flow can handle. It is also a very meaningful project demonstrating building a high-performance processor with complete open-source technologies from architecture, RTL to GDSII possible.

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RIOS Lab Released the Official Test Suite Standard for RISC-V Vector Extension at RISC-V Summit

RISC-V 2022 North America Global Summit

The four-days RISC-V 2022 North America Global Summit was held in San Jose, California, December 12th-15th, 2022. The conference schedule includes:

· RISC-V members day meeting

· RISC-V Future Watch featuring breaking news on products, technology, ecosystem expansion, etc.

· Technical and industry topics meetings

· Innovative research presentation

Automatic Test Generation and Verification for RISC-V Vector Extension, from RISC-V International Open Source (RIOS) laboratory, was admitted by RISC-V Summit North America 2022. Dr. Wang Yi and Mr. Hu Shenwei were honored to attend the conference as speakers and had an in-depth discussion online to communicate with industry professionals.

The RISC-V Vector Extended Instruction Set (RVV) version 1.0 has been introduced for high-performance execution of vectorized computing. However, the RVV introduces 217 new instructions, seven new CSRS, and seven configuration parameters. The complexity makes it difficult for developers to produce a test suite, especially because of the number of different RVV parameter configurations (vlen, vsew, vmul, etc.) that combine with each other.

To solve this problem, RIOS Lab, in collaboration with the RISC-V Foundation, designed an RVV test generator for RISC-V community that can be configured with a combination of parameters. We first designed and implemented the RVV Sail Model as the golden model for executing RVV instructions. With Sail model ‘s support, we further developed a configurable test generator that generates quantifiable coverage test sets for RISC-V vector extensions. The user can select the instruction to be tested, set the configuration parameter combination, and then automatically generate the associated tests.

The whole process of test production and usage is compatible with the latest RISCOF toolchain and can be tested simultaneously with vector extension and other extension test sets in the same environment. We also demonstrated our RVV support for RISCV-ISAC and RISCOF to obtain quantitative coverage reports.

Currently, the Sail RVV adaptation has pushed the Pull Request to the official repository and is being checked by RISC-V Foundation. The test generator and RISC-V ISAC are undergoing final feedback and adjustment with RISC-V  Foundation, and it will be released soon after the improvement.

Original link:

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RIOS Lab Students Gave a Talk at the RISC-V Days Tokyo, 2022

RISC-V Days Tokyo

RISC-V Days Tokyo is the largest physical and online RISC-V event held in Japan. The purpose of RISC-V Days Tokyo is to bring together the leading RISC-V technologies and products, key persons and engineers in the industry, and to provide opportunities for product recognition, collaboration among companies, technology exchange and information gathering. Participants will have the chance to explore the latest RISC-V products and technologies, network with key industry figures, and learn about the latest developments in RISC-V technology. Overall, RISC-V Days Tokyo promises to be an exciting opportunity for anyone interested in RISC-V technology.

Our student Zhu Yifei gave a talk “GreenRio: A modern RISC-V microprocessor designed entirely in an agile open source EDA flow” at the RISC-V Days Tokyo. The booming  RISC-V and open-source EDA ecosystem lower the threshold for CPU design. To facilitate a reliable chip manufacturing flow and prepare for future agile development, our students constructed a full-stack design methodology for modern processors in an open-source mode based on our experience in the efabless MPW-7 shuttle. We developed a 64-bit dual-issue, out-of-order RISC-V microprocessor “GreenRio”, and completed the back-end process of “RTL-Verification-GDS-Signoff” purely depending on the open-source EDA toolchain. we will share our experience and provide a complete set of tape-out strategy for modern RISCV processors from ASIC front-end to back-end. We will also propose some innovations and adaptations based on existing open resources. Moreover, we will compare commercial and open-source EDA tools from a modern processor design perspective, with the limitations and future optimizations of the open-source tool summarized.

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